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Ventana Micro Systems Inc. today debuted a new data center processor, the Veyron V1, that is based on the open-source RISC-V instruction set architecture.
Ventana claims that the Veyron V1 is the first RISC-V processor capable of matching the performance provided by the most widely used data center chips. Additionally, the startup says that its silicon can also be used in other areas. Ventana envisions companies deploying the Veyron V1 in systems ranging from vehicles to 5G networking devices.
“Our vision of delivering the highest performance RISC-V CPUs is helping to reshape next generation high performance open hardware architectures,” said Ventana founder and Chief Executive Officer Balaji Baktha. “Today, we have a significant first mover advantage by providing a platform that can allow customers to innovate and differentiate.”
Ventana launched from stealth mode last September with $38 million in funding. It designs chips based on the RISC-V instruction set architecture, which was developed at the University of California, Berkey in 2010. The architecture has gained significant industry traction over the past few years.
By default, a processor can only perform a limited number of computing operations. Those computing operations are in many cases fairly simple. However, the processor can mix and match them in a way that allows complex calculations to be performed
The simple computing operations that a chip mixes and matches to carry out calculations are known as instructions. Engineers implement them using a blueprint known as an instruction set architecture, or ISA. The ISA also defines other technical details, such as what types of data a chip can work with.
RISC-V is an pre-packaged ISA that chip design teams can use to implement the instructions of a new processor and define related technical details. It’s distributed for free under an open-source license. Because it’s available at no charge, RISC-V enables chip companies to avoid the costs associated with licensing a proprietary ISA from a company such as Arm Ltd.
The new Veyron V1 chip that Ventana debuted today is the first in a series of RISC-V processors the startup plans to launch. It features 16 cores capable of operating at a clock frequency of 3.6 gigahertz. The cores are supported by 48 megabytes of onboard L3 cache.
Ventana has equipped its chip with reliability optimizations as well as support for virtualization, which enables servers to operate more efficiently. Additionally, the startup says the Veyron V1 includes features for blocking side channel attacks. A side channel attack is a type of hacking campaign in which technical data about a chip, such as its power usage, is used to find ways of delivering malware or stealing data.
According to Ventana, the Veyron V1 is implemented as a chiplet. A chiplet is a compact computing module that can be integrated with other types of processors. A company could, for example, build a processor that combines Veyron V1 cores with other computing modules such as artificial intelligence accelerators.
Ventana says that multiple Veyron V1 chiplets can be linked together to build a system-on-chip with up 192 cores. According to the startup, its silicon can enable companies to develop new processors up to two years faster than would otherwise be possible and at a 75% lower cost.
Image: Ventana
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